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Features
* Low-voltage and Standard-voltage Operation * * * * * * * * * * * * *
- 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Automotive Devices Available 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Two-wire Serial EEPROM
1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra T hin Mini-MAP (MLP 2x3) , 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. 8-lead TSSOP 8-lead SOIC Table 1. Pin Configuration
Pin Name A0 - A2 SDA SCL WP NC GND VCC Function Address Inputs Serial Data Serial Clock Input Write Protect No Connect Ground Power Supply 8-ball dBGA2
VCC WP SCL SDA
8 7 6 5 1 2 3 4
16K (2048 x 8)
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
AT24C01A(1) AT24C02(2) AT24C04 AT24C08A AT24C16A(3)
Notes: 1. Not Recommended for new design; Please refer to AT24C01B datasheet. 2. Not Recommended for new design; Please refer to AT24C02B datasheet. 3. Not Recommended for new design; Please refer to AT24C16B datasheet
A0 A1 A2 GND
8-lead Ultra Thin Mini-MAP (MLP 2x3)
VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND
Bottom View 8-lead PDIP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
Bottom View 5-lead SOT23
SCL GND SDA 1 2 3 4 VCC 5 WP
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1
Absolute Maximum Ratings
Operating Temperature..................................-55C to +125C Storage Temperature .....................................-65C to +150C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
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Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground. The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground. The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground. WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled and operates as shown in Table 2. Table 2. Write Protect
WP Pin Status At VCC At GND Part of the Array Protected 24C01A Full (1K) Array 24C02 Full (2K) Array 24C04 Full (4K) Array 24C08A Full (8K) Array 24C16A Full (16K) Array
Normal Read/Write Operations
Memory Organization
AT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing. AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.
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Table 3. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
Table 4. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC ICC ISB1 ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.5V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 Test Condition Min 1.8 2.7 4.5 0.4 2.0 0.6 1.4 1.6 8.0 0.10 0.05 Typ Max 5.5 5.5 5.5 1.0 3.0 3.0 4.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 Units V V V mA mA A A A A A A V V V V
1. VIL min and VIH max are reference only and are not tested.
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Table 5. AC Characteristics Applicable over recommended operating range from TAI = -40C to +85C, VCC = +1.8V to +5.5V, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
1.8-volt Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
2.7, 5.0-volt Min Max 400 1.2 0.6 Units kHz s s 50 0.1 1.2 0.6 0.6 0 100 0.9 ns s s s s s ns 0.3 300 0.6 50 5 5 1M s ns s ns ms Write Cycles
Min
Max 100
4.7 4.0 100 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 4.5
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time(1) Inputs Fall Time(1) Stop Setup Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Byte Mode
1M
1. This parameter is characterized.
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Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition.
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Bus Timing
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O(R)
Write Cycle Timing
Figure 3. SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT WORDn
ACK
twr STOP CONDITION
Note:
(1)
START CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
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Figure 5. Start and Stop Definition
Figure 6. Output Acknowledge
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Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11). PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.
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ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 10 on page 12). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).
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Figure 7. Device Address
MSB
8K 16K
Figure 8. Byte Write
Figure 9. Page Write
(* = DON'T CARE bit for 1K)
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Figure 10. Current Address Read
Figure 11. Random Read
(* = DON'T CARE bit for 1K) Figure 12. Sequential Read
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AT24C01A Ordering Information(1)
Ordering Code AT24C01A-10PU-2.7(2) AT24C01A-10PU-1.8(2) AT24C01A-10SU-2.7(2) AT24C01A-10SU-1.8(2) AT24C01A-10TU-2.7(2) AT24C01A-10TU-1.8(2) AT24C01A-10TSU-1.8(2) AT24C01AU3-10UU-1.8(2) AT24C01AY1-10YU-1.8(2) (Not recommended for new design) AT24C01AY6-10YH-1.8(3) AT24C01A-W1.8-11(4) Notes: Package 8P3 8P3 8S1 8S1 8A2 8A2 5TS1 8U31 8Y1 8Y6 Die Sale Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
1. This device is not recommended for new design. Please refer to AT24C01B datasheet. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. "U" designates Green Package + RoHS compliant. 3. "H" designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 8Y6 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Away Package (dBGA2) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V)
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AT24C02 Ordering Information(1)
Ordering Code AT24C02-10PU-2.7 AT24C02-10PU-1.8(2) AT24C02N-10SU-2.7(2) AT24C02N-10SU-1.8(2) AT24C02-10TU-2.7(2) AT24C02-10TU-1.8(2) AT24C02Y1-10YU-1.8(2) AT24C02-10TSU-1.8(2) AT24C02U3-10UU-1.8(2) AT24C02-W2.7-11(3) Notes:
(2)
Package 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 5TS1 8U3-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
1. This device is not recommended for new design. Please refer to AT24C02B datasheet. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. "U" designates Green Package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Away Package (dBGA2) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V)
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AT24C04 Ordering Information(1)
Ordering Code AT24C04-10PU-2.7 AT24C04-10PU-1.8(2) AT24C04N-10SU-2.7(2) AT24C04N-10SU-1.8(2) AT24C04-10TU-2.7(2) AT24C04-10TU-1.8(2) AT24C04Y1-10YU-1.8(2) (Not recommended for new design) AT24C04Y6-10YH-1.8(3) AT24C04-10TSU-1.8(2) AT24C04U3-10UU-1.8(2) AT24C04-W1.8-11(4) Notes: 1. 2. 3. 4.
(2)
Package 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 5TS1 8U3-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. "U" designates Green Package + RoHS compliant. "H" designates Green Package + RoHS compliant, with NiPdAu Lead Finish. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 8Y6 5TS1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8-ball, die Ball Grid Away Package (dBGA2) Options -2.7 -1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V)
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AT24C08A Ordering Information(1)
Ordering Code AT24C08A-10PU-2.7 AT24C08A-10PU-1.8(2) AT24C08AN-10SU-2.7(2) AT24C08AN-10SU-1.8(2) AT24C08A-10TU-2.7(2) AT24C08A-10TU-1.8(2) AT24C08AY1-10YU-1.8(2) (Not recommended for new design) AT24C08AY6-10YH-1.8(3) AT24C08AU2-10UU-1.8(2 AT24C08A-W1.8-11(4) Notes: 1. 2. 3. 4.
(2)
Package 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 8U2-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. "U" designates Green Package + RoHS compliant. "H" designates Green Package + RoHS compliant, with NiPdAu Lead Finish. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 8Y6 8U2-1 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 8-ball, die Ball Grid Array Package (dBGA2) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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AT24C16A Ordering Information(1)
Ordering Code AT24C16A-10PU-2.7 AT24C16A-10PU-1.8(2) AT24C16AN-10SU-2.7(2) AT24C16AN-10SU-1.8(2) AT24C16A-10TU-2.7(2) AT24C16A-10TU-1.8(2) AT24C16AY1-10YU-1.8(2) (Not recommended for new design) AT24C16AY6-10YH-1.8(3) AT24C16AU2-10UU-1.8(2) AT24C16A-W1.8-11(3) Notes:
(2)
Package 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 8U2-1 Die Sale
Operation Range
Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
1. This device is not recommended for new design. Please refer to AT24C16B datasheet. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. "U" designates Green Package + RoHS compliant. 3. "H" designates Green Package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 8Y6 8U2-1 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 8-ball, die Ball Grid Array Package (dBGA2) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN - NOM - MAX NOTE
A A2 b b2 b3 c D
0.210 0.195 0.022 0.070 0.045 0.014 0.400
-
2
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240
0.130 0.018 0.060 0.039 0.010 0.365
-
5 6 6
3 3 4 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.310 0.250 0.100 BSC 0.300 BSC
0.325 0.280
Side View
4 0.150 2
0.115
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
18
AT24C01A/02/04/08A/16A
0180Z-SEEPR-11/06
AT24C01A/02/04/08A/16A
8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
19
0180Z-SEEPR-11/06
8A2 - TSSOP
3
21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
20
AT24C01A/02/04/08A/16A
0180Z-SEEPR-11/06
AT24C01A/02/04/08A/16A
8Y1 - MAP
PIN 1 INDEX AREA
A 1 2 3 4
PIN 1 INDEX AREA
E1 D D1
L 8 E A1 b 7 6 5 e
Top View
End View
Bottom View
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
A
A A1
MIN - 0.00 4.70 2.80 0.85 0.85 0.25
NOM - - 4.90 3.00 1.00 1.00 0.30 0.65 TYP
MAX 0.90 0.05 5.10 3.20 1.15 1.15 0.35
NOTE
Side View
D E D1 E1 b e L
0.50
0.60
0.70
2/28/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 DRAWING NO. 8Y1 REV. C
R
21
0180Z-SEEPR-11/06
8Y6 - Mini-MAP (MLP 2x3 mm)
A
D2
b (8X)
Pin 1 Index Area E2 E
Pin 1 ID L (8X)
D A2 A3 A1
e (6X) 1.50 REF.
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D E D2 E2 A A1 A2 A3 L e b 0.20 0.20 1.40 0.0 MIN NOM 2.00 BSC 3.00 BSC 1.50 0.02 0.20 REF 0.30 0.50 BSC 0.25 0.30 2 0.40 1.60 1.40 0.60 0.05 0.55 MAX NOTE
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 Dual No Lead Package (DFN) ,(MLP 2x3) REV. C
R
22
AT24C01A/02/04/08A/16A
0180Z-SEEPR-11/06
AT24C01A/02/04/08A/16A
5TS1 - SOT23
e1 5 4 C
E1
E
C L
L1 1 2 3
Top View
End View
b
A2
A
Seating Plane
e D
A1
Side View
NOTES: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-193, Variation AB, for additional information. 2. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 mm per side. 3. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. 4. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 5. Dimension "b" does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. The Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. SYMBOL A A1 A2 c D E E1 L1 e e1 b
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.00 0.70 0.08 NOM - - 0.90 - 2.90 BSC 2.80 BSC 1.60 BSC 0.60 REF 0.95 BSC 1.90 BSC 0.30 - 0.50 4, 5 MAX 1.10 0.10 1.00 0.20 4 2, 3 2, 3 2, 3 NOTE
6/25/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 5TS1, 5-lead, 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SHRINK SOT) DRAWING NO. PO5TS1 REV. A
R
23
0180Z-SEEPR-11/06
8U2 - dBGA2
E
D
Pin 1 Mark this corner
Top View
- Z-
8 7 6
1 2 3 4
Ob
0 0 . . 1 0 5 8 M M Z Z X Y
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE
#
#
D D1 E
#
5.10 1.43 TYP 3.25 1.25 TYP 0.75 TYP 0.75 TYP 0.90 REF 0.49 0.35 0.47 0.52 0.38 0.50 0.55 0.41 0.53
#
d
5
E1 e d
D1 E1 e
A2 A A1
A A1 A2
Bottom View Side View
Ob
Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information. 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z.
02/04/02 DRAWING NO. REV. A
TITLE
R
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
8U2, 8-ball 0.75 pitch, Die Ball Grid Array Package (dBGA) AT24C512 (AT19870)
8U2
24
AT24C01A/02/04/08A/16A
0180Z-SEEPR-11/06
AT24C01A/02/04/08A/16A
8U3-1 - dBGA2
E
D
1.
b
PIN 1 BALL PAD CORNER
A1 A2 A
Top View
PIN 1 BALL PAD CORNER
Side View
4
1 (d1)
2
3
d
8 e
7
6
5
COMMON DIMENSIONS (Unit of Measure = mm) (e1) SYMBOL MIN 0.71 0.10 0.40 0.20 NOM 0.81 0.15 0.45 0.25 1.50 BSC 2.00 BSC 0.50 BSC 0.25 REF 1.00 BSC 0.25 REF MAX 0.91 0.20 0.50 0.30 NOTE
Bottom View
8 SOLDER BALLS
A A1 A2 b
1. Dimension "b" is measured at the maximum solder ball diameter. This drawing is for general information only.
D E e e1 d d1
6/24/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) DRAWING NO. PO8U3-1 REV. A
R
25
0180Z-SEEPR-11/06
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
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2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
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0180Z-SEEPR-11/06

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